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october 2010 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate 74AUP1G57 tinylogic ? low power universal configurable two- input logic gate features ? 0.8v to 3.6v v cc supply operation ? 3.6v over-voltage tolerant i/os at v cc from 0.8v to 3.6v ? high speed t pd - 2.9ns: typical at 3.3v ? power-off high-impedance inputs and outputs ? low static power consumption - i cc =0.9a maximum ? low dynamic power consumption - c pd =2.9pf typical at 3.3v ? ultra-small micropak? packages description the 74AUP1G57 is a universal configurable 2-input logic gate that provides a high performance and low power solution ideal for battery-powered portable applications. this product is designed for a wide low voltage operating range (0.8v to 3.6v) and guarantees very low static and dynamic power consumption across the entire voltage range. a ll inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. the 74AUP1G57 provides for multiple functions as determined by various configurations of the three inputs. the potential logic functions provided are and, nand, or, nor, and xnor, inverter and buffer. refer to figures 2 to 8. ordering information part number top mark package packing method 74AUP1G57l6x ab 6-lead micropak?, 1.0mm wide 5000 units on tape & reel 74AUP1G57fhx ab 6-lead, micropak 2?, 1x1mm body, .35mm pitch 5000 units on tape & reel
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 2 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate pin configurations 1 b 2 gnd 3 6 5 4 a c v cc y figure 1. micropak? (top through view) pin definitions pin # name description 1 b data input 2 gnd ground 3 a data input 4 y output 5 v cc supply voltage 6 c data input
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 3 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate function table inputs 74AUP1G57 c b a y=output l l l h l l h l l h l h l h h l h l l l h l h l h h l h h h h h h = high logic level l = low logic level function selection table 2-input logic function conn ection configuration 2-input and figure 2 2-input and with both inputs inverted figure 5 2-input nand with inverted input figure 3, figure 4 2-input or with inverted input figure 3, figure 4 2-input nor figure 5 2-input nor with both inputs inverted figure 2 2-input xnor figure 6 inverter figure 7 buffer figure 8
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 4 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate 74AUP1G57 logic configurations figure 2 through figure 8 show the logical functions that can be implemented using the 74AUP1G57. the diagrams show the demorgan?s equivalent logic duals for a given two-input function. the logical implementation is next to the board-level physical implementation of how the pins of the function should be connected. b y c b y c 1 2 3 6 5 4 b y c v cc b y c b y c 1 2 3 6 5 4 b y c v cc figure 2. 2-input and gate or 2-input nor with both inputs inverted figure 3. 2-input nand with inverted b input or 2-input or gate with inverted c input a y c a y c 1 2 3 6 5 4 a y c v cc a a y c a y c 1 2 3 6 5 4 y c v cc figure 4. 2-input nand with inverted c input or 2-input or gate with inverted a input figure 5. 2-input nor gate or 2-input and gate with both inputs inverted b y c 1 2 3 6 5 4 y c v cc b 1 2 3 3 6 5 4 y v cc y a a figure 6. 2-input xnor gate figure 7. inverter 1 2 3 6 5 4 y v cc y b b figure 8. non-inverter buffer
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 5 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 4.6 v v in dc input voltage -0.5 4.6 v v out dc output voltage high or low state (1) -0.5 v cc + 0.5 v v cc =0v -0.5 4.6 i ik dc input diode current v in < 0v -50 ma i ok dc output diode current v out < 0v -50 ma v out > v cc +50 i oh / i ol dc output source / sink current 50 ma i cc or i gnd dc v cc or ground current per supply pin 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature, soldering 10s +260 c p d power dissipation at +85c micropak-6 130 mw micropak2-6 120 esd human body model, jedec:jesd22-a114 5000+ v charged device model, jedec:jesd22-c101 2000 note: 1. i o absolute maximum rating must be observed. recommended operating conditions (2) the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage 0.8 3.6 v v in input voltage 0 3.6 v v out output voltage v cc =0v 0 3.6 v high or low state 0 v cc i oh /i ol output current v cc =3.0v to 3.6v 4.0 ma v cc =2.3v to 2.7v 3.1 v cc =1.65v to 1.95v 1.9 v cc =1.4v to 1.6v 1.7 v cc =1.1v to 1.3v 1.1 v cc =0.8v 20.0 a t a operating temperature, free air -40 +85 c ja thermal resistance micropak-6 500 c/w micropak2-6 560 note: 2. unused inputs must be held high or low. they may not float.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 6 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate dc electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units min. max. min. max. v p positive threshold voltage 0.80 0.30 0.60 0.30 0.60 v 1.10 0.53 0.90 0.53 0.90 1.40 0.74 1.11 0.74 1.11 1.65 0.91 1.29 0.91 1.29 2.30 1.37 1.77 1.37 1.77 3.00 1.88 2.29 1.88 2.29 v n negative threshold voltage 0.80 0.10 0.60 0.10 0.60 v 1.10 0.26 0.65 0.26 0.65 1.40 0.39 0.75 0.39 0.75 1.65 0.47 0.84 0.47 0.84 2.30 0.69 1.04 0.69 1.04 3.00 0.88 1.24 0.88 1.24 v h hysteresis voltage 0.80 0.07 0.50 0.07 0.50 v 1.10 0.08 0.46 0.08 0.46 1.40 0.18 0.56 0.18 0.56 1.65 0.27 0.66 0.27 0.66 2.30 0.53 0.92 0.53 0.92 3.00 0.79 1.31 0.79 1.31 v oh high level output voltage 0.80 v cc 3.60 i oh =-20a v cc -0.1 v cc -0.1 v 1.10 v cc 1.30 i oh =-1.1ma 0.75 x v cc 0.70 x v cc 1.40 v cc 1.60 i oh =-1.7ma 1.11 1.03 1.65 v cc ? 1.95 i oh =-1.9ma 1.32 1.30 2.30 v cc 2.70 i oh =-2.3ma 2.05 1.97 i oh =-3.1ma 1.90 1.85 3.00 v cc 3.60 i oh =-2.7ma 2.72 2.67 i oh =-4.0ma 2.60 2.55 v ol low level output voltage 0.80 v cc 3.60 i ol =20a 0.10 0.10 v 1.10 v cc 1.30 i ol =1.1ma 0.30 x v cc 0.30 x v cc 1.40 v cc 1.60 i ol =1.7ma 0.31 0.37 1.65 v cc ? 1.95 i ol =1.9ma 0.31 0.35 2.30 v cc 2.70 i ol =2.3ma 0.31 0.33 i ol =3.1ma 0.44 0.45 2.70 v cc 3.60 i ol =2.7ma 0.31 0.33 i ol =4.0ma 0.44 0.45 i in input leakage current 0v to 3.6v 0 v in 3.6 0.1 0.5 a i off power off leakage current 0v 0 (v in ,v o ) 3.6 0.2 0.6 a i off additional power off leakage current 0v to 0.2v v in or v o =0v to 3.6v 0.2 0.6 a i cc quiescent supply current 0.8v to 3.6v v in - v cc or gnd 0.5 0.9 a v cc v in 3.6 0.9 i cc increase in i cc per input 3.3v v in =v cc -0.6v 40.0 50.0 a
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 7 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate ac electrical characteristics symbol parameter v cc conditions t a =+25c t a =-40 to +85c units figure min. typ. max min. max. t phl , t plh propagation delay 0.80 c l =5pf, r l =1m 22.1 ns figure 9 figure 10 1.10 v cc 1.30 2.5 6.5 12.6 2.5 13.0 1.40 v cc 1.60 2.2 4.6 7.6 2.2 8.2 1.65 v cc 1.95 2.0 3.9 6.2 2.0 6.8 2.30 v cc 2.70 1.7 3.1 4.5 1.7 5.1 3.00 v cc 3.60 1.3 2.9 3.9 1.3 4.1 0.80 c l =10pf, r l =1m 27.1 1.10 v cc 1.30 3.2 7.6 14.4 2.8 14.9 1.40 v cc 1.60 2.6 5.3 8.7 2.8 9.3 1.65 v cc 1.95 2.2 4.6 7.0 2.2 7.8 2.30 v cc 2.70 1.9 3.7 5.2 1.9 5.9 3.00 v cc 3.60 1.3 2.8 4.6 1.3 4.9 0.80 c l =15pf, r l =1m 32.6 1.10 v cc 1.30 3.4 8.3 15.7 3.1 16.7 1.40 v cc 1.60 2.8 5.8 9.4 3.1 10.4 1.65 v cc 1.95 2.5 5.1 7.9 2.5 8.7 2.30 v cc 2.70 2.1 4.0 6.1 2.1 6.9 3.00 v cc 3.60 1.3 3.2 5.0 1.3 5.5 0.80 c l =30pf, r l =1m 25.4 1.10 v cc 1.30 3.4 8.6 18.5 3.4 19.0 1.40 v cc 1.60 3.1 5.5 10.5 3.1 11.0 1.65 v cc 1.95 2.1 4.5 8.7 2.1 9.5 2.30 v cc 2.70 1.5 3.4 6.9 1.5 7.4 3.00 v cc 3.60 1.1 2.9 5.9 1.1 6.3 c in input capacitance 0 0.8 pf c out output capacitance 0 1.7 pf c pd power dissipation capacitance 0.80 v in =0v or v cc , f=10mhz 1.8 pf 1.10 v cc 1.30 1.82 1.40 v cc 1.60 1.85 1.65 v cc 1.95 1.9 2.30 v cc 2.70 2.1 3.00 v cc 3.60 2.9
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 8 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate ac loadings and waveforms figure 9. ac test circuit figure 10. ac waveforms symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v 1.5v 0.10v 1.2v 0.10v 0.8v v mi v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v mo v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 9 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate physical dimensions 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 11. 6-lead, micropak?, 1.0mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 10 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 65 4 0.35 (0.08) 4x side view figure 12. 6-lead, micropak2?, 1x1mm body, .35mm pitch package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G57 ? rev. 1.0.4 11 74AUP1G57 ? tinylogic ? low power universal confi gurable two-input logic gate

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